What is Dark Silicon?

Recent advancements relating to transistor size reduction in technology has fuelled an unprecedented growth in the number of transistors available in microprocessor systems. As a result of this, the number of cores have increased drastically resulting in performance enhancement. Unfortunately, this size reduction increases the power consumption and consequently causes thermal damages, a term many denote as Dark-Silicon. In Dark-Silicon systems, only a fraction of cores can powered-on per time and thus open up many opportunities as well as challenges for providing high performance within an allowable power budget. For this purpose, many multi-core chip blueprints require focus not only on the performance but thermal properties such as hotspot, ageing whilst considering a power budget.

Consequently, this opens up a whole field of exploration to improve the fraction of activity in multi-core systems. Fortunately, there are many ways this can be done. Example of these are Application mapping, Network-on-Chip (NoC) power optimisation (Buffers, Crossbars) and Cache Power optimisation. 

  • The Network-on-Chip (NoC) paradigm has replaced the traditional bus-based systems as the standard interconnect for many-core systems. However, NoC consumes a staggering amount of power and therefore requires configuration in its components for continuous advancement. A reduction of power in NoC components will result in a drastic decrease in overall system power. 
  • Application Mapping – In the dark silicon era, application mapping can be beneficial because it can used to select the appropriate resources for an application to be executed. Applications mapping can be executed in two ways: Contiguous mapping and Non-contiguous mapping. Contiguous mapping is done by mapping application tasks to cores around the same region to prevent communication overheard. Unfortunately, this mapping can sometimes result in thermal hot spot caused by the heat generated by neighbouring resources. Non-contiguous mapping on the other hand causes latency among tasks as resources are randomly mapped across the whole chip. Therefore, a balanced algorithm which considers both these issues is required for an optimised performance.
  •  The introduction of the Last-Level Cache to close down the gap between the memory and processor has resulted in an increase in the total cache power. This is because, Cache memories are created from SRAM Technology which consumes a lot of power. This is means the bigger the memory, the more power it is consumes. LLC’s are bigger in size and thus consumes a lot of power. However, this can be decreased by using Non-volatile memory such as STT-RAM.  

Moreover, for an optimised many-core system, designers needs to consider several stipulations. The fraction of active resources in a dark-silicon many-core system depends not only the power budget provided, it also depends on the appropriate number of activated cores, the thermal hot spot generated during run-time and the amount of power consumed by working components.